Using HLS synthesis to design FPGA based video processing core

OData support
Supervisor:
Szántó Péter
Department of Measurement and Information Systems

The 1970s saw very early research work in high-level synthesis but the usable solutions appeared only in the early 2000s. Nowadays a lot of development environments are available that can be used to generate a high quality HDL implementation from C based specification along with the directives adjusting the operation of the hardware.

The high-level synthesis provides the benefit to complete the design at a higher abstraction level in a shorter time. Describing the specification in a C based language software developers can also create FPGA based applications. Xilinx Vivado HLS is the pioneer of the modern HLS tools. The subject of this diploma thesis is the evaluation of the possibilities of Vivado HLS through the implementation of a polyphase video scaler.

The diploma thesis begins with the review of the basic characteristics of Vivado HLS. It is examined through a simple processing unit, i.e. Gauss-filter, how highly parallel hardware structure - that is able to accept input data in every clock cycle - can be generated. Next the polyphase video scaling algorithm is described. I detail the implementation and simulation of the video scaler core in Vivado HLS environment that can process arbitrary resolution both at its input and output. A demo design on the Digilent Atlys board is created for testing the core on real hardware. The configuration of the scaler is done by a Microblaze processor embedded in the FPGA. Finally, I summarize my experiences about the high level synthesis tool of Xilinx and the results of my master thesis.

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