Development of high level arithmetic processor by FPGA.

OData support
Supervisor:
Dr. Max Gyula
Department of Automation and Applied Informatics

High-perforamnce processors rely on fast arithmetic modules for mathematical computing. From the four basic arithmetic operation the division is in the centre of this thesis. The dividers are the slowest of all the basic arithmetic operations in digital computation because of their complexity. The adders, subtractors and multipliers in the arithmetic moduls reach far higher performance. The need for high-speed hardware dividers is present in many applications.

Two types of dividers were created for the arithmetic module. Integer dividers were develepod based on restoring and not-restoring division algorithm. The divider based on restoring division is a sequential divider and it requires less area as opposed to the pipe-lined divider based on not-restoring division. However the pipe-lined divider guarantee a higher throughput and hereby it is capable of higher performance. A floatin-point divider form the other division part of the arithmetic module based on Taylor series algorithm. The implementation of a floating-point divider is usually more elaborate and demands careful rounding and normalizing by reason of the representation.

Both divider types were written in Verilog HDL. The dividers were developed and tested in FPGA environment. The floating point divider suited well to the FPGA environment. Embedded multipliers and RAM memory from the FPGA were used to create the whole division structure of the floating point divider.

Downloads

Please sign in to download the files of this thesis.