Development of a Master JTAG unit

OData support
Supervisor:
Dr. Fehér Béla
Department of Measurement and Information Systems

The rapid development of digital circuits increased the complexity of modern circuits significantly. Post-production testing of high density printed circuit boards nowadays are more and more difficult. Instead of outdated methods modern tools and techniques were needed in testing of printed circuits.

The testing of circuits has always been an essential part of the production, so it is not surprising that Design for Testing became the leading policy among manufacturers. In the early 90s, arrival of Boundary Scan (JTAG) technology brought the solution to testing of integrated circuits which is now the most widely used method for testing, debugging and programming as well.

In the first half of my thesis I present the IEEE 1149.1 standard and the SVF file format that consists boundary scan vectors to be sent to a device under test. Then I introduce the developed Master JTAG unit and its associated software which can be used to perform essential testing and debugging tasks on devices under test.

Downloads

Please sign in to download the files of this thesis.