In my thesis I present the expansion of an application-specific instruction-set processor (ASIP) with accelerator unit. An accelerator unit like this has the task to perform a complex operation of the processor, taking over its time-consuming task. I implemented matrix operations to my accelerator unit.
I implemented the register transfer level (RTL) model of the unit by a hardware description language (HDL), and verificated its function with simulations of the independent model. After that I inserted it into the RTL model of the processor, completed the functional verification there also, and compared the running times of assembly programs for different algorithms. In the end I synthesized the model onto FPGA (Field Programmable Array) , checked its resource requirements, completed the static timing analysis, and based on these informations I made suggestions for the future development and modifications, which can guarantee the efficiency of the processor on algoritms consisting matrix operations.