Memory coherence protocol multi-processor systems

OData support
Supervisor:
Dr. Kollár Ernő
Department of Electron Devices

My thesis project is about the cache coherence problem present in multiprocessor architectures and the cache coherence protocols that solve the issue. In my thesis I define the coherence problem, present the knowledge necessary for designing cache coherence protocols, and propose a coherence protocol designed by myself.

I first present an overview of cache memories, including a more detailed description of cache associativity and caching strategies. These details are especially important, because they define how the coherence protocol should deal with certain events. Then I offer a summary of the cache coherence protocols. I write about some special considerations for designing multi-core systems (multiprocessor ideologies, memory hierarchies), the archetypes of coherence protocols, and different approaches to maintaining memory coherence. I provide a detailed description of the MESI coherence protocol as it the type of protocol used in my own system.

The implementation of the shared memory is of key importance in multiprocessor architectures. I summarize the relevant information in two chapters about shared memory consistency models and different types of memory implementation. Shared memory consistency models deal with the strictness of the sequential consistency requirement in a multi-core system. The memory implementations introduced have radically different approaches to maintaining cache coherence than the traditional coherence protocols.

After the description of the theoretical background I present the system I designed. In the overview chapter I describe the events handled by the architecture, the states and transitions of my MESI coherence protocol, the chosen memory hierarchy, and the general role of the system's modules. I designed the coherence protocol for an 8-core architecture with scalability in mind. The directory based coherence protocol I use is appropriately scalable for further cores.

The key elements of the architecture are the cache memories, the cache memory controllers, the shared memory, and the coherence controller. The coherence protocol is implemented by the cache memory controllers and the coherence controller, which are described in detail in separate chapters. The simulation results verifying the proper operation of the protocol are also presented in a separate chapter. The simulations are grouped by the instructions handled by the coherence directory and its supplementary logic.

I designed the system by using the Verilog hardware description language. The simulations were also done by HDL testbenches.

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