In our modern world large-scale integration of electronic devices can be observed in the everyday life. No wonder, then, if today's society has higher expectations to the industry. The growing user demand and market competition, encourage manufacturers to develop more and more complex digital circuits with shorter deadlines, whose reliability has become a cardinal issue because of the high requirements.
The functional verification provides a solution for this problem, which aim is to perform reliable and quick testing of circuit designs or higher level abstraction models. The base of this process is to develop an automated environment around the circuit model, which allows random test vectors to generate, and perform exhaustive testing in order to ensure complete reliability.
This process is supported by so called verification languages and methodologies appeared as a result of standardization efforts.
The aim of my thesis work is to demonstrate the functional verification process with the support of the "e" verification language and UVM methodology.