Design of a high-frequency data acquisition module

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Lazányi János Gyula
Department of Measurement and Information Systems

The objective of my thesis is to design the architecture, the schematics and the printed circuit board (PCB) of a high-speed (250 MSamples/s) data acquisition I/O module for the Compact RIO (cRIO) Programmable Automation Controller (PAC) of National Instruments (NI).

cRIO is an embedded, reconfigurable control and acquisition system powered by graphical programming tools for rapid prototyping. It is extendable with several modules, such as servo motor controller modules, CAN communication modules, general purpose I/O modules, data acquisition modules etc.

The sampling frequency of the currently available modules designed for examination of analog signals does not exceed 1 MS/s. In the meantime, there are many applications where higher sampling frequency is needed, such as radar-based applications, examination of modulations or high-speed digital signals, 2.5G and 3G cellular basestation transceivers, satellite and GPS receiver interfaces. My project is motivated by the fact that a module with a sampling rate of hundreds of MS/s can be a significant improvement. The most likely reason for the lack of such a module is that the cRIO bus can only supply no more than 1 W of power per module which is clearly not enough for the subjected functionality. Only the power consumption of the FPGA chip embedded into the module exceeds this limit. Therefore, the price payed for the high rate capability is that the desired power has to be fed by an external power supply into the module.

The designed data acquisition card receives two analog input signals through some of four SMA connectors of its front panel. It is programmable whether the input signals are single-ended or differential, hence the four connectors. High-bandwidth relays serve as switches between the two types of inputs. The input signals are both AC-coupled.

After filtering, decoupling and amplifying the signals, they are sampled at a maximum rate of 250 MS/s by an Analog-to-Digital Converter (A/D converter, ADC). The digital samples are fed through an FPGA chip and are stored in a DDR3 memory. The FPGA preprocesses (primarily decimate) the stored signals and it sends the preprocessed data to the cRIO central module via the cRIO backpane bus. The cRIO central module will be able to feed the stream to a computer (e.g. PC or another cRIO) via Ethernet where it will be post-processed with the NI LabView software. The two digital streams require a throughput of 500 MBytes/s, each, while the cRIO bus is capable of no more than 40 MBytes/s, which motivates local decimation of the data within the module. For proper functionality, the module needs five levels of supply voltage.

Amplification is performed by a Variable Gain Amplifier (VGA) chip whose gain is set by an analog voltage signal controlled by a Digital-to-Analog Converter (D/A converter, DAC).

The chosen A/D converter chip that samples the signals provides two channels. AC signals can be measured in the range of 0 to 2 Vpp at a resolution of 16 bits. By using the maximum 20 dB amplification of the VGA, the input range can be decreased to 0.2 Vpp while the resolution becomes ten times better.

The FPGA was primarily selected on the grounds of operating frequency, the required number of differential I/O pins, cost. In the meantime, integrated memory controller in the FPGA was required in this application. According to these requirements the Xilinx Spartan-6 XC6SLX75 FPGA in an FGG484 Ball-Grid-Array (BGA) package is finally used in the design.

The schematics of the module is drawn in the Pads 9.0.1 Logic software of Mentor Graphics, while the PCB is designed in Pads Layout and Pads Router.


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