Development of Microprocessor Architecture

OData support
Supervisor:
Dr. Hosszú Gábor
Department of Electron Devices

In this thesis I present a heterogeneous system architecture, that integrates a general purpose processor (CPU) and a graphical processor (GPU). The CPU core implements the ARMv2 ISA (Instruction Set Architecture). The ARMv2 is an early version of the ARM instruction set, witch can be freely implemented as its not protected by patents. Even though its old, the instruction set is highly efficient and supported by many open source compilers. The possibility to implement it without breaking any patents, its high efficiency and the fact that many highly optimized compilers still support it makes it an ideal choice for research and develop projects. The graphical core implements a simple fixed function rendering pipeline, the primary purpose during its development was to be used in GPUGPU tasks.

In this thesis after detailing the instruction set architecture and microarchitecture of general purpose processors, I will examine the inner structure and working of graphical processors, and I will also present the advantages of heterogeneous system architectures. After the theoretical overview I will present the CPU and the GPU of the heterogeneous architecture, developed for this thesis. I will also present the tools developed for the processor along with the compiler toolchain itself, and the verification of the design through simulations.

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