Leading edge FPGA technology makes debugging even harder. Logic Analyzers and Real-Time Debug Tools require external hardware and software setup which may not be available for the developer. RTL simulation requires the engineer to have a good insight of the design as well as the internal signals and the design is not implemented on hardware, so there might be some run-time errors that can not be detected by this technique.
During my work I have developed a configurable FPGA debugger logic which is capable of monitoring signals inside the FPGA and is widely usable in systems based on WISHBONE bus due to its parameterized nature. The module implements trigger functions which control stimuli based on in-system events or data without the need for re-synthetizing the design.
I have created a WHISBONE SLAVE interface to connect the debugger module to the WISHBONE system. The SLAVE is not only capable of executing WISHBONE bus cycles, but is prepared for the fact that the debugger is highly parameterized while WISHBONE address and data signals have fixed size.
To control the capture and logging data, I have written a TCL script, so the appropriate behaviour of the system could be verified.