This thesis considers the issues of the analog integrated circuit’s physical design, the designing of the analog layout. Below the 250nm technology node, if not addressed properly several physical effects can cause serious problems in the circuit design. These effects are called the layout dependent proximity effects. Through literature review I summed up the theoretical backgrounds of these effects, and how they impact transistor performance.
Variation in the circuit’s performance induced by these effects can only be identified via layout extraction and post-layout simulation. The circuit may require redesigning, if the post-layout simulation with the extracted parameters fails to meet the specification’s requirements. This causes extra work for the circuit and layout designer and greatly increases design time.
With the Cadence integrated circuit design system I designed test-circuits upon which I performed post-layout simulations. With these simulations the design corners can be identified and used in the earlier steps of the circuit design. The ruleset is made through these design corners which can help minimize the layout dependent proximity effects at an early design stage.
After the simulations I designed the layout of the complete test-circuit chip, and made it ready to manufacture. The simulation results can be checked by measurements on the test chip, the ruleset then can be refined.