In the packet-switched networks, time synchronization has always been a hot topic. Nowadays there are several solutions for synchronization, like the most recent IEEE 1588v2, where high precision time stamping system is a basic requirement.
In this Thesis an FPGA-based time stamping framework is presented, which is capable of time stamping with high-precision the incoming packets in wired and wireless networks. In the wireless subsystem the timing parameters of the timing estimation method is used, thereby reaching nanosecond accuracy. In parallel with this a time stamping method is presented for wired networks, which can operate from the recovered clock provided by Synchronous Ethernet chip thus giving a much more accurate time stamp.
Another advantage of the time stamping system is that the use of the FPGA and the modular framework structure provides an environment, where the development of existing modules and the implementation of new functionality are very easy.
The implemented system can be used for time synchronization purposes in wired and wireless networks, as the precision of the time stamping module highly satisfies the requirements of IEEE1588v2.