Most of the modern digital integrated circuits operate synchronously. It means the operation of the building blocks and cells and the realization of proper communication between different subparts (e.g.: within a datapath) of the circuits demand appropriate clock signal. It is getting more difficult to achieve the clock signals arrive to the subparts of the integrated circuit in time. Clock signals are typically loaded with the greatest fan-out, travel over the longest distances, and operate at the highest speeds of any signal, either control or data, within the entire system.
Different clock signal paths can have different delays for a variety of reasons (different length, different number of the connected gates, etc.). If a difference of the arrival time of different clock signals appears (clock skew) the functional operation of the whole circuits can be failed.
Nowadays a new type of global clock distribution systems is under focus: Injection Locked Oscillator based clock distribution system. In this case the global reference clock signal is generated on the central point of the die, and is distributed to the local centers. In each local centers there are ILO circuits, which can synchronize to the incoming global clock signal.
in this thesis the operation and built-up of modern clock distribution systems, the phenomenon of clock skew, the design steps of a ring oscillator based ILO circuits and its simulation results will be presented. The design steps and the simulations were carried out under the Cadence OPUS IC 6.1.4 design framework. The circuit was optimized to the AMS 0.35µm CMOS process.