The multicore systems are more and more used in FPGA circuits and the performance of these systems is very depends of the data communication between the processor cores. Widely used shared memory and common bus system based communication solutions can not be used effectively with large processor numbers, so appeared the Network on a Chip systems, which creates a communication network inside the FPGA chip to ensure data exchange between different devices.
My goal was to create a Network on a Chip generator, which could be parameterized in a wide scale, thus it is able to create an optimal NoC system in the terms of resource utilization and performance, depending on the application area. The basic element of the NoC system is the Crossbar, which can be used to create a network of arbitrary topologies and implement packet based communication between the endpoints.
The parameters of the Network on a Chip generator can be the following: network topology, number of endpoints, word size of the message words and the maximum length of packets. The system currently supports five topologies - unidirectional and bidirectional ring, star, mesh and torus - but it is easy to develop new ones depending on user needs.
Furthermore, the Crossbar's input arbitration (fixed or RoundRobin) and the number of storable messages are also configurable, therefore the number of parallel handled messages can be large.
To develop the Network on a Chip generator, I needed a hardware description language, which supports to create parameterizable hardware, so my choice was on MyHDL Python based HDL language.
The secound part of this master thesis I made the verification of the created NoC system in UVM framework, to create this I used the EasierUVM code generator. The EasierUVM generates standard UVM system, so it creates a verification system, which can be used to verificate my own Network on a Chip system, but with a little bit of modification it is suitable to test all NoCs.