In our days hardware design is such a complex process, that even with the aid of widespread HDLs (Hardware Description Language), it is an extremely difficult task to create an easily understandable and functionally correct description of a hardware (with non-trivial functionality).
Due to this problem, verification of the completed hardware or even the hardware under design is necessary. During the verification process we check if the hardware meets the requirements of the specification. Though in a typical case is very important after a design process to demonstrate to the customer or to our company that the design meets the requirements indeed, on the other hand it can be just as usefully during the design process, because if applied well, it reveals the errors in the current design continuously, so they can be localized and fixed on spot. At the end of the process fixing them would consume significantly more resources, because they would appear indirectly and in some cases affect the whole design.
In former times designers used simple test benches for this purpose but it is very difficult to apply them during a bigger verification project. For this application modern verification languages were developed, such as SystemVerilog, SystemC, e, VERA, etc. These are – according to the modern trends – object orientated languages.
But simply applying these does not grant a unified and reusable verification methodology, so biggest companies in the market developed their own methodology. Then in 2008 two big companies (Cadence and Mentor Graphics) worked together and developed OVM (Open Verification Methodology). This is an open-source SystemVerilog library, which is a very effective and reusable verification methodology.
My thesis introduces this methodology through a simple example.