FPGA-based PSI5 communication protocol controller

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Supervisor:
Dr. Horváth Péter
Department of Electron Devices

The aim of this thesiswork is to design an interfacecontroller module, which is able to connect

to an under development measurement device. That device will be able to measure the PSI5 conformity

of any circuit, which communicates with this protocoll.

As a first step during writing this thesis, I familiarised myself with the PSI5 standard, which is

a two-wire data interface working with current modulation. It is normally used for one-way communication,

but two-way is also possible. In this case, the Slave device sends data to the controller

with Manchester coding on the current line. The Master unit communicates on the voltage line

using pulses with defined length and amplitude.

After getting to know the protocol, the next step was selecting an FPGA device capable of

implementing the interface contoller. An important aspect was that a high-precision ADC with

high sampling frequency had to be part of the system, for exact decoding. This requirement greatly

limits choices. Furthermore, for flexibility and compatibility with other applications, the choice

had to be a device which is connected to a processor system. Based on the above aspects, the chosen

device was the Xilinx Zinq 7000 FPGA. This chip contains an ADC of which the resolution and

and sampling speed is not suitable for measurements which have to be conducted by the system

containing the interface controller designed in this paper. Several constructions offered themselves

to solve this. The two most advantageous ones are presented in Chapter 2. The final decision was

to use the Redpitaya StemLab 125-14 board, as it contains an appropriate ADC, and also a DAC,

which is needed during synchronous operation of the protocol, and two-way communication, so

that the controller can send out the synchronous pulses.

The next step was design of the system. Decoding from sampled signal flow was solved here,

as well as the ability of the system to send out voltage pulse sequences according to the communication.

To realise the latter, the circuit written in the programmable logic is connectable to the

microprocessor in the SoC. The voltage sample to be sent can thus be given to the control unit.

After implementing the system plan, the correctness of operation was confirmed with logical

simulations, taking into account that the HDL model should be synthesisable.

The hardware device has its own linux operating system. To communication with the board

can be done via serial port and also ethernet, without using any external module or program.

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