At first, a brief explanation of the title can provide insight into the detailed contents, so I begin with presenting my thesis with that.
The second part of the title, namely “10Gbps Ethernet Video Extender”, refers to a new market product under development which will be able to transmit all types of recent digital (DVI, HDMI, SDI, HD-SDI, 3G-SDI, Display port) and analogue (VGA, DVI-I) video signals.
By using this new product, incoming signals are transformed into 60 bit wide parallel pixel bus – which can support any kind of video format - by using dedicated video ICs. The product measures the pixelclock on the source-side, and re-creates it on the remote-side according to the transmitted data.
The product is capable of transmitting not only video signals but any kind of audio signals supported by I2S audio standard, which means that it supports the audio formats from two-channel PCM to DolbyTrueHD. The transmission medium can be optical fiber or copper cable. The communication with 10 Gbps speed uses the Ethernet 802.3ae standard.
The targeted task within the frame of this thesis is to adapt many different low-speed, parallel processing peripheries into this system under development, and I also aim to apply a common interface to interlace these data streams. The interlaced data together with the video and audio signals are transmitted by using Ethernet packages. At the remote side, at first, the interlaced data is splitted by a module I have developed. Secondly, data is directed to their own peripherals. The first part of the thesis title, namely “Parallel Multi-Protocol Module Planning”, refers to the above-mentioned data processing.
In the final design we are going to integrate one or more of the following peripherals into the system: serial port (RS-232), infrared data transmission, DMX (transmission based on RS-485), KVM (Keyboard-Video-Mouse, transmission by USB), 10/100/1000Mbps Ethernet. These peripherals can be used by the user optionally.
I have developed both the receiver and the transmitter modules, furthermore an interlacer module and it’s inverse (de-interlacer) during the development process.