The throughput divided by the power consumption is one of the key metrics in modern telecommunication networks. Besides being very efficient for computation intensive applications, FPGAs might be the competitors of the currently used network solutions due to their low specific power consumption. Their advantage is that they can process the network traffic at line rate which lets the software manipulate the filtered packets and the FPGA logic itself may also execute some of the operations.
In this work, the aim was to design a universal pattern matching FPGA module that is able to set an alarm when the data packets the meet pre-defined conditions. This operation is the base of network packet filtering. From the different methods of pattern matching, regular expressions provide the most powerful way because of their variety and compactness. Therefore, implementing them in hardware was the main task to achieve. The created design can be used without any limitations on the packet switched network type. The target criteria included the maximization of line rate capability and the minimization of FPGA resource allocation. Looking for possible applications also helped to evaluate the characteristics of the designed IP core. Consequently, the results also involve an investigation of the usability of FPGA based pattern matching on top of creating a diversely applicable building block.