Pipeline image processing with partially reconfigurable FPGA

OData support
Supervisor:
Raikovich Tamás
Department of Measurement and Information Systems

This thesis is based on two main topics. One of them is the image processing pipeline, which provides the applicable functionality for the user. The other topic is how such a system can be implemented on a partially reconfigurable FPGA device.

It is very common in digital image processing applications to do a set of modification techniques after each other on the image subject to processing to get the result reqired by the application. There is plenty of applications in practice, for example positioning and quality control in industrial environment, image enhancement and manipulation in media industry, advanced driver assistance systems in transport, etc. Most of these techniques can see can be parallelized, and sped up with the use of specialized hardware. The speed gain can be significant compared to what is capable with multi-core CPUs. Parallelization is performed on two levels. The first level is provided inherently by executing the processing units of the pipeline at the same time. The second level is achieved inside these processing units. The FPGA provides a platform that is suitable for this type of implementation. In this thesis I present the implementation of a reconfigurable pipeline on FPGA. This sytem can be configured flexibly and swiftly to the of the requirements of the image processing task. Besides that, it also profits from the parallelization possibilities of the FPGA to speed up execution. The hardware platform is a Kintex-7 based PCI Express compatible extension card. The system can be operated with the the user application. It hides the PCE Express communication, the control of the pipeline and the FPGA reconfiguration. The user application provides a simple interface for the user to select and apply the image processing methods.

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