During the course of the semester I examined the possibility of creating a pipeline processor in an FPGA. I did extensive research about processors that contain some form of instruction pipelining and got acquainted with the pitfalls and difficulties of designing a processor with a pipeline.
Using this knowledge I choose a processor architecture which I implemented using a Hardware Description Language (Verilog). I later extended the instruction processing of the design to include a simple 4-stage pipeline which theoratically should allow a higher instruction throughput, resulting in a significant improvement to the processor's performance.
The designed processor was then tested extensively using a logic analyzer and several test programs that were written in assembly. Once the design was deemed working the performance impact of the pipeline was tested and measured.
The end result is a design that fits entirely inside most modern FPGA's without exhausting the given devices resources, thus providing a soft core microprocessor with improved performance that can be useful for other projects.