This document is an M.Sc thesis about the usage of SystemC virtual platforms in software and hardware developing tasks.
It introduces the possibilities of the high level, SystemC-based hardware-software codesign, and the abstraction levels of the SystemC.
It shortly describes the transaction level system modelling (TLM), and the details of the timing of TLM modules, and the use of temporal decoupling
for the acceleration of TLM-based simulations.
It explains the ways for
increasing the performance of a virtual platform by hardware acceleration methods. Describes the realization of the communication between
the different hardware and software components, and its possibilities for improval. For achieving greater simulation precision, it introduces
a way to synchronize the components. It introduces the hardware equivalent of the TLM temporal decoupling.
It briefly shows the sources of the inaccuracy in the use of the hardware accelerated virtual platform, and shows ways to solve them.
It proves the increased performance of the system with measurements.