CPU frequency scaling of softcore processors

OData support
Supervisor:
Wacha Gábor József
Department of Measurement and Information Systems

My thesis describes the process of preparing a MicroBlaze-based soft core processing system implemented for Atlys Spartan 6 FPGA and modifying the runtime clock signal with a chosen peripheral. The peripheral I utilized was a ’DIP’ switch. During the development process, I used a development environment supported by Xilinx (XPS, SDK, Adept, ChipScope).

My expectation was that by increasing/decreasing clock signal frequency, the power consumption of the FPGA would increase/decrease as well. To achieve this, I prepared a frequency divider module, which enabled me to control the clock signals of the system I had created. The frequency was changed by a C based MicroBlaze program, running on the processor. I chose the 30MHz and 75 MHz frequencies for my research, and the results were recorded with the Adept program (developed by Diligent).

Then, I examined how the power consumption results varied in time. I found that at the moment of setting the switch to 1 (this option indicates a switch to a 75 MHz clock signal), the power consumption values of the FPGA multiplied with almost 1.5. I drew the conclusion, that I managed to reach the goals I set for this project. The results proved that altering the clock signal does not have an effect on the functioning of the ’basic’ peripherals.

I think that it would be worth the effort to explore this topic in greater depth, for example by building a more advanced system involving a Linux distribution. In this system, we could change the clock signal by a predefined command. To achieve this, we would have to prepare a so-called Clock Governor in the Linux kernel.

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