Implementing a Rasterizer Unit on FPGA

OData support
Supervisor:
Szántó Péter
Department of Measurement and Information Systems

Rasterizer module realization in FPGA circuit

This MSC thesis task is the design and implementation of a 3D graphics rasterizer component. This module can be a part of a later designed full graphics processor unit. The rasterization process implements the screen to pixel transformation, and the visibility testing.

The thesis starts with bibliography research, during which I learnt about 3D rendering approaches and exact techniques, from which I focused on incremental rendering and tile based rasterization the most, for these are being used in my rendering solution. The work includes the development of a component’s early version testing and implementing, and its further development.

The later stage of development started with research on the practical requirements of a rasterizer, during which I got to know an open source driver, in order to acquire data that can be processed. I also wrote a script for the raw information’s processing in Matlab. The detailed information on the rasterizer module allows the redesign of the components, to achieve a better optimized version. Finalizing, implementing and testing this version are to be the end of the thesis work.

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