SHA cryptographic algorithm implementation on FPGA

OData support
Supervisor:
Dr. Fehér Béla
Department of Measurement and Information Systems

In today’s computer engineering, with the ever increasing amount of data, that we store or share digitally, cryptography becomes an important factor. It is important that we find fast and secure ways to ensure, that our data is only accessible by the right party. Cryptographic hash functions provide authentication and integrity. Such functions take a finite data input and compress it to a given length message digest.

One of the biggest challenges for current cryptographic applications are not sufficient data throughput and the fast development of hashing algorithms. While hardware implementations provide a good data throughput, every change in the algorithm comes with a complete change of hardware. Field Programmable Gate arrays mean an alternative solution to this problem, thanks to their reconfigurable nature.

This work presents a high performance FPGA implementation of SHA-256 algorithm. The main target is to create a simple basic architecture, that achieves the highest possible data throughput, while maintaining an easy-to-integrate, device independent, SHA-256 core. The implementation provides a 7.75 bit/cycle solution, which means roughly 600 Mbit/s throughput at a frequency of 80 MHz for a Xilinx Spartan6 XC6SLX9 FPGA.

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