Nowdays, technology is developing in a very high rate. This causes the evolution
of equipment used in video technology. Due to this and higher expectation of quality,
digital transmission gradually replaced analog technology.
In professional applications it is common to have more sources and displays.
Signals can be transmitted to longer distances in many kinds of interfaces. One
of the most commonly used digital audio transmission standards is the S/PDIF
(Sony/Philips Digital Interface Format). In this case data must be coded before
transmitting on high-speed media as embedded audio. It is important to ensure
that audio timing can be recovered on receiver side, even if the transmission is
asynchronous. It requires that an appropriate clock data recovery circuit should be
implemented in the receiver stage.
Due to their parallel architecture, FPGAs can be used effectively in digital signal
processing, for example audio and video processing. They have been gaining traction
in high performance applications because of their speed and precision. FPGAs
can be reprogrammed to desired application or functionality requirements after
manufacturing. This feature distinguishes FPGAs from ASICs and reduces the time
of development and overall non-recurring engineering costs. Manufacturers offer
DSP-optimized FPGAs containing DSP slices to increase performance and speed.
AXI protocol is used as a standard interface to connect components that wish to
exchange data. It is commonly used in FPGAs. The aim of my thesis is to transmit
decoded S/PDIF data across AXI4-Stream interface with the recovered clock signal.