Nowadays it is really impotant that, during the digital circuit design, the implemented hardware should be able to perform the required operation without any disfunctionality. To reach this, we have to use high-level functional verification before these designs go to the factory.
In my thesis work, I will explain what is the functional verification and its type. I mention the fact that the individual types have different adventages and disadvantages. During my thesis I was getting familiar with the ’e’ Hardware Verification Language. I will give a short intrudoction about the fundamentals of the ’e’ coding and ’e’ code running process. As the functional verification methods became more and more complex, it has become increasingly necessary to systamize them. The result of this process the standardized methodologies. During this 1 year work, I got acquainted with the e Reuse Methodology (eRM) which is based on the ’e’ language and after that the improved and more regular Universal Verification Methodology (UVM).
I will introduce the elements of the verification environment specified by the UVM, how they work and how to implement them following the basic UVM recomendations and guidelines. To do my work I used an SPI controller HDL implementation which was implemented under my Project Laboratory II in previous semester. The SPI is based on the Freescale IC manufacturerers SPIV3 specification. I will give a short intrudoction of the main features and the structure of the controller.
From the functional specifications I created the verification plan and I built up the verificataion envirnoment. I will show the designing process of the SPI controller’s verification environment as well as the implementation of the functional checks and the coverage items. I will introduce the built environment’s structure and operation of the bigger components, and emphasize the major steps.
I have written the test sequences which was important for covering the test scenarios. The behavior of these tests will be detailed. I ran all the implemented tests, what is called regression. After the regression I have analyzed the results and I give a summary of the found HDL disfunctionalities and possible way of fixing these bugs. At the end of my thesis I will rate my 1 year project and draw conclusions.