My goal was to study the generation of clock trees and create a clock tree in my demo processor. First I extended the processor with indirect jump and call instructions, then I synthesized the Verilog code and designed the layout of the chip. I compared the the timing of the synthesized netlist and of the layout and I found serious differences in the results. As it turned out the RTL Compiler (synthesizing tool) and the Encounter Digital Implementation System (EDI, layout designer tool) used different library. After I had corrected the configuration script, the difference shrank, but did not disappear completely.
I found other differences between the results of the RTL Compiler’s timing analysis and the simulation waveform. The timing analysis underestimated the worst path’s time delay, when I specified high frequency timing constraint. Unfortunately I could not find any explanation for this data mismatch.
I learned from the user guide of the EDI, that it supports two modes of clock tree snythesis, the automatic clock tree synthesis (CTS), and the manual CTS. Automatic CTS mode creates a clock tree best suiting the given timing constraint. The user specifies the buffer cells that can be used, and the timing constraint, the CTS does the rest of the work. The user can define a clock tree topology with manual CTS mode (number of the levels, buffer type on each level).
I gave EDI a timing constraint (defined the clock period), and specified the buffer cells on the GUI. EDI generated a specification file with CTSTCH extension. This file includes all data necessery for the CTS, so I could modify and use it later on.
The manual CTS mode required a specification file as well. I chose the net that I wanted to replace with the tree, and specified the topology.
I tested the clock trees, and compared the results (clock phase delay, clock skew).
This work will help to synthesize a clock distribution system with the use of an injection locked oscillator (local clock distributor) developed by other students.