When I started working on this thesis, my main goal was to get a basic understanding of how FPGAs work, and how to program them using a Hardware Description Language (HDL), in my case Verilog. Never really having prior knowledge of these subjects, I felt I needed to build it from the ground-up. Designing a calculator seemed like and interesting task, which allowed me to have a better understanding of implementing basic arithmetics in a digital system, using an FPGA.
The need for devices compatible with decimal operations are getting higher and higher, as for example, the financial sector requires such high precisions calculations, where binary representations doesn’t suffice.
Although, a calculator may sound like a simple device, considering how widespread it is, but implementing not only BCD arithmetics, but floating-point support and calculating results up to 16 significants is a very resource-intensive task.
My implementation of this stack based calculator is able to add, subtract, multiply and divide on signed 16 digit significand numbers, with and exponent from -383, up to 384. It uses the Reverse Polish Notation, thus making the stack based operations simple. Writing of the stack must happen from the outside of the module, requiring a control unit of some sort.
The designing of said device allowed me to have a better insight on implementing a simple system on an FPGA, and to have a better understanding of realising decimal arithmetics on a digital device.