In this thesis I have investigated the effectiveness of one of the most well-known SystemC based high-level synthesis tool, the Cadence C-to-Silicon software. For the purpose, I have implemented a mathematical transformation, the discrete cosine transform, which contains sufficient number of operations, though it is not too difficult. First of all, I have chosen the best algorithm for testing purposes on the basis of the available literature, then I have implemented it in SystemC language. The behavior of the description has been validated in a test environment created using MatLab. I have created five microarchitectures in RTL level using C-to-Silicon. These have been synthesized using Cadence Encounter RTL Compiler software, and the generated pre-layout structures have been compared by chip area, timing and power consumption. The optimal microarchitectures also have been redesigned manually in RTL level using SystemVerilog hardware description language. These have been synthesized too and compared to structures generated by C-to-Silicon, pointing out the advantages and disadvantages of HLS design flow.