Synthesizable Test Environment for Hardware-Accelerators of an Applications-Specific Instruction Set Processor

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Dr. Horváth Péter
Department of Electron Devices

More and more digital systems are used in everyday life recently. Due to the market competition the function and the reliability of these systems have to be checked continously. Before the product enters the market, it has been already checked by a long process called verification. Verification is a very complex process, which has to be done correctly to save costs to the company, cause every device has a different reliability and quality requirement. That’s why many different tools are used during the verification of each product. But in some cases an universal tool is needed, which can be used in the verification of the designs with similar structure but with different function. This can reduce the verification time and cost and support the reusability as well. This summary includes the first phase of development of a synthesizable testbench for the accelerator units of an application specified instruction-set microprocessor, and its advantages and disadvantages. The document includes an abstract from the bibliography of the verification, the requirement specification, the system design and the validation of the testbench, and some consideration about the following development.


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