In the world of hardware description languages, the two most widely used are the Verilog and the VHDL. Both of these are perfect for modeling digital systems and logical functions, however the resulting models’ correctness has to be checked and verified. For this purpose, they often use another language, a hardware verification language, which provides all the functions that a sophisticated and an overall verification procedure may require. In cases of that kind, they invoke e.g. the SystemVerilog language, which derived a lot of syntactical element from the C and the C++ programming languages, hereby it supports the system-level designing and verification processes in one single standard.
With my work, I would like to demonstrate that SystemVerilog, which is mostly used for verification purposes, also copes with synthesizing digital systems. To prove the suitability of it, I have developed and implemented a microprocessor system in SystemVerilog: during my work I have highly relied on the syntax and the simplifications that can be found in the language.