Design of an FPGA-based Stereo Video Splitter Device

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Kovács Viktor
Department of Automation and Applied Informatics

The scope of this thesis is to design and verify an FPGA based system, which purpose is to receive HDMI data, store it and then split it to two VGA adapters. In addition to this, the paper also deals with programming a microcontroller to receive and write data to an EDID EEPROM, which is used to communicate the capabilities of the display to the computer connected to it.

In the first part, I will be presenting the history of the project; I will talk about the basic concept and show a problem with the current construction.

In the second part, I will be going through the VGA, HDMI, EDID, I2C and UART standards. The goal for this is section is to show a small insight into the inner workings, methods of operation used by displays in our everyday lives and to demonstrate what capabilities and parameters they have. During the presentation of the EDID standard, I will be going through the data structure, explain its contents and the possible options. During the I2C section, I will talk about the general usage of this protocol and after that, I will show a more specific use, which will be writing and reading an EEPROM.

In the next section, I will introduce a printed circuit board designed to solve the problem, which is affecting the use of the demonstration tool, show, talk about its design, and elaborate on all the major integrated circuits present on the boar

During the last part, I will be presenting my own work, which fulfills the criteria mentioned above. First, I talk about generating the data, which will be written into the EDID EEPROM. After that, I introduce the software I have built for the microcontroller to receive this data and write it to the memory. Lastly, I will discuss the modules written for the FPGA. Since the printed circuit was defectively assembled, I could not test these on the board, so I had to resort to simulating the input on the FPGA.


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