Nowadays in the development of logic circuits become more and more important question of size reduction. It follows many physical barriers, especially the dissipation. In the new way, the elements of logic circuit made of special materials, which could control the dissipated heat and react to a sharp decrease in resistance, while increasing the temperature. Such a material is Vanadium-dioxide, what we can use creating Thermal-Electronic Logic Circuit.
In this paper, I am going to introduce the methodes of TELC, the structures of proposed layers, and open up vistas of Lift-off and wet etching process.
Before my work, I summerize the exercises and results, what I did in the laboratory last semester.
I have designed test structure of different sizes with a layout editor, which name is CleWin4, focusing on the limits of size reduction. Then, I took part in the realization and set the parameters in the laboratory of Budapest University of Technology and Economics, Department of Electronic Devices. I have measured on samples, and evaluated them.