Implementation of a content encryption algorithm using FPGA

OData support
Supervisor:
Szántó Péter
Department of Measurement and Information Systems

Like many other industries the use of standard Ethernet networks is becoming more common in audio-visual data distribution. As opposed to traditional Pro AV

environments, AV over IP refers to the use of existing IP-based equipment to transmit and switch video and audio signals. This requires special transmitter and

receiver units like Lightware’s UBEX optical extender family which allows packet based media transmission.

Since audio and video is moved from a separated network to a LAN or WAN carrying other user data the security of critical data must be ensured. Data encryption is a suitable method to this privacy issue.

Symmetric-key algorithms can be used more efficiently for encrypting high bandwidth data like video while the key required for this process can be transmitted using a public-key method which is more complex. AES is a widely used symmetric-key algorithm in these applications due to its performance and security level. It is considered to be efficient both for hardware and software implementations because the iterative structure allows scalability in terms of speed and resource utilization.

The inherent parallelism of the algorithm using pipelined architecture can be efficiently exploited in FPGAs which makes it possible to reach a very high speed

required to serve the media streams. Security issues also make FPGA implementations more advantageous as they are, by nature, more physically secure.

Cryptographic algorithms and their associated keys that are implemented in hardware cannot easily be read or modified.

This paper presents an FPGA implementation of the pipelined AES encryption process which is designed to be able to serve more media streams using unique keys.

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