Having studied the literary sources for external and internal logical analyzers, as well as guides describing the operation of SignalTapII and ChipScope, I came up with the requirement specification and the system design for the integrated logic analyzer. I have prepared the RTL model, verified it in an automated regression testing HDL environment and then synthesized it on FPGA technology. Finally, I've added a graphical user interface to make the configuration simpler. So I got a working FPGA prototype, which I tested in a real circuit environment.
By the end of the semester, I managed to design an integrated logic analyzer with minimal resource requirements and technological independence to allow to be used on any manufacturer's FPGAs. Additionally, it can be configured for inputs and trigger conditions in synthesis time, and for sampling frequency, sampling type, edge detection of the trigger conditions, the connection of the trigger conditions and selecting the input signals at run time.