Design framework for application-oriented microprocessors

OData support
Supervisor:
Dr. Hosszú Gábor
Department of Electron Devices

The hardware description languages developed to describe the behavior of complex digital systems make possible analyzing and designing hardware tools at different levels of abstraction. The increasing complexity forced the design methodologies to move to a higher abstraction level [1]. In the 2000s, the so-called electronic system-level (ESL - Electronic System Level) paradigm was evolved including the system-level description languages (C, C++, SystemC etc.) and the high-level synthesis tools (SystemCrafter, CatapultC etc.), which are able to transform an algorithmic model into a gate-level description. When we design an application-specific system, the methodologies and tools of the ESL paradigm are unavoidable, but in case of instruction-set processor design the main abstraction level is so far the so-called register-transfer level [2].

The aim of my work was to integrate the benefits of high-level synthesis and application-specific processor design. In this paper I present a newly developed mixed-level digital modeling language called ARTL (Algorithmic RTL), an ARTL-based design methodology and a design framework that integrates them. The advantage of this approach is that the time consumption of the design process can be much more favorable.

In the second part of this paper, a new FPGA-optimized microprocessor architecture is presented, which fits well with the ARTL language constructs and therefore it is capable to implement diverse application specific instruction sets. This architecture is called process-controlled machine.

In the third part of the paper a complete design framework is presented that includes all of the software tools developed to aid ARTL-based processor design.

At the end of this paper three process-controlled machines are presented that were developed with the discussed methodology and software tools. I tested these microprocessors in a simulation environment and I also implemented them into an FPGA circuit. The functional correctness of the processors and the favorable time consumption of the design process proves the applicability and the efficiency of the developed design methodology.

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