Parasitic analysis has a significant role in designing of power electronics systems. The analysis does not only contain the derivation of parasitic effects related to the manufacturing technology of components, but also the layout related parameters, too. The collective of these parasitic effects fundamentally determine the power dissipation and the switching processes of the circuits.
Power dissipation is linked with the parasitic resistances. The switching loss provides an upper limit, and the inductances appearing in the system provide a lower limit to the switching times. The induced voltage peaks appearing in the moments of switching due to the latter, are not allowed to exceed the critical characteristic values of the components, because it can cause their breakdown. When breaking the high currents of power electronics circuits, the induction caused by the parasitic effects always have to be considered.
In this diploma thesis, like the part of a design process, I overview the applicable methods for parasitic analysis. I focus on the layout related parasitic effects. Getting experience in use of ANSYS Q3D Extractor finite element software was also my goal, because according to my assessment, it provides the most realistic modelling of parasitic effects.
I introduce the methods through the example of a classic half-bridge topology. This circuit is simple to design, but is also representative, because a typical switching procedure can be observed through its example. The half-bridge circuit is realized with three different topologies, on printed circuit boards.
Finally, I compared the results of parasitic analysis based on different methods with the parameters of the measured characteristics during real operation. The output of my work is a methodology of parasitic analysis based on finite element field simulation, that is able to be used in future projects.