The Universal Asynchronous Receiver/Transmitter or UART is a computer hardware designed
for implementing the interface for serial communications. The UART is capable of
converting data between its parallel and serial forms. Serial transmission is commonly used
with modems and for non-networked communication between computers, terminals and other
My thesis is about designing a UART that has full-duplex communication capabilities.
Full-duplex communication means that the hardware can receive and transmit data on its
serial input and output.
The thesis is broken down into four main parts, that match the stages of the design
process. These parts are:
• Functional Specification
The goal of creating this specification is getting a general overview of the UART.
This section deals with the expected features and limitations of the hardware. A general
structure is created for the design, including the modules that will be implemented.
Another important part of this section is the overview of the reception and transmission
processes with their expected paths and timings.
• Architecture Specification
The Architecture Specification is much more in-depth than the functional one. It
contains all the information necessary for properly coding the UART. This information
includes the input/output tables and schematics of each module. A brief functional
description is provided for every module and the main design units inside them. This
specification is not hardware description language specific, so the design outlined by it
can be coded using any language. The language chosen by me is Verilog.
• Verification Plan
This section is about the simulation environment. It describes the structure of the
Testbench and details the requirements of properly simulating the Device Under Test.
The specified goals of the test cases are also listed here.
• Simulation Results
The waveforms of the most important test cases are presented here. It contains the
explanations of these waveforms and the achieved functionality.