Today’s digital devices are generally using dynamic memory to store data and program code. Advantage of this technology is the large storage capacity due to simple architecture, however - because of this simple architecture - each memory cell has to be refreshed by a specific interval, otherwise the content will be lost.
By increasing the standardized refresh period, the number of the bit errors will be growing. One goal of another research in our department to find correlation between number of bit errors measured with non-standardized refresh periods and physical condition of examined memory chips. Initially, measurements were running practically on FPGA platform, the idea is to create a PC based platform to serve the measurements. Difficulties are coming from the requirement that we need to test the main memory of the PC, therefore the program cannot be running there.
The Unified Extensible Firmware Interface (UEFI) specifies the interface between the operating system and the PC hardware, UEFI was developed as replacement of Basic Input/Output System (BIOS). In case of creating a custom BIOS/UEFI firmware including the memory testing algorithm, it could be executed from a separated flash memory to test the main memory. Goal of this thesis to create this platform.