In the past two semesters I have made my degree related work by Evosoft Hungary Kft.. My thesis presents the standard and universal verfication methodology called UVM with the use of e verification language by Cadence. All of these are presented with a real project where a bridge module developed by Xilinx has been fully verified.
My thesis introduces the functionality of ARM protocols (AXI4 and AHB-Lite) used by the bridge module and the specification of the module. On the basis of these I have worked out the verification plan fit for my task. Keeping the plan in mind I have built up the whole verification environment and presented it with all of my considerations. Through situated code parts in my thesis I introduce the use of e verification language and the related technics which allowed me to make a universal and automated verification environment.
At the end my thesis presents the definition of test cases and an analysis about their results. Eventually I have found three functional errors with the help of my verification environment. The conditions and details of these errors have been presented with the help of waveforms.