Nowadays the sizes of the integrated circuits are so large that checking the functionality is so complex, it is not possible to perform it manually. The market had a fast reaction to this problem, thus more and more tools and methodologies appeared during the years to come up with a solution. In this paper I introduce some of these tools and methodologies through an example verification project.
In the first part of this paper I introduce the classification of the several verification methods. I list the advantages and disadvantages of the different types of simulation-based verification, about what their purposes are. After that I write about formal hardware verification, what kind of tools are available and how to use them. Lastly I discuss the assertion-driven verification, which is the combination of the previously mentioned methods.
In the second part I introduce the UVM methodology. I discuss the setup of the verification environment, the folder structure and the know-hows of the developing process that help to create an easily understandable, reusable environment.
In the final part I show the verification process on the HDL design of an AXI-SPI bridge, using the methods listed above. In the first few sections I write about the preparation of the verification process and the planning of the environment. Finally I list the implementation details, starting from the environment setup, through the reference models, to the testing of the final code.