FPGA design methods without recompilation

OData support
Supervisor:
Wacha Gábor József
Department of Measurement and Information Systems

Nowadays, the big FPGA integrated circuits can implement complex digital circuits. What’s more the designs have become more and more complicated. The designs have to be compiled to get the FPGA image. The compiler is optimizing the source files in several steps, however it has two drawbacks. The first disadvantage is that this compiling and optimizing can takes hours. Another problem is that the whole FPGA image can change due to some small design modifications.

Because of the complex circuits the probabilities of mistakes in the design has increased. The fixing of these mistakes has become more and more complex. Generally we have to make modifications in the design and we have to recompile this design in order to get a new FPGA image which is suitable find the mistakes. Usually this recompile runtime is as long as the original compile. Moreover, it is possible that the new image does not contain the searched mistake, due to the wholly new physical image; however, we did not fix the mistakes in the source files.

In my essay, I give solutions for the above mentioned problems. One part of the methods is based on the fact, that several parts of the image can be unmodified; therefore the runtime can be reduced. Another part of the methods can preserve the previous physical image; therefore it guarantees that the mistake is embedded in the partly new image.

I worked with Xilinx FPGA-s and development environment. So first of all the solutions connected to this vendor.

Downloads

Please sign in to download the files of this thesis.