The topic of my thesis is the analysis of the semiconductor to metal phase transition of the vanadium dioxide thin film. This phase transition makes possible to create Thermal-Electronic Logic Circuits (TELC). The significance of this is that the complexity of the silicon-based integrated circuits can be increased on a same area with TELC, instead of the further size reduction in the CMOS technology. The size reduction in today's CMOS technology is becoming more and more challenging, because there are physical limits of the technology, which will be achieved soon. The purpose of my thesis was to detect what differences can be observed on the C-V (capacitance-voltage) curves by temperature change, and how the phase transition of vanadium dioxide effect on them. Firstly, in my thesis, I presented the techniques of C-V measurement, then I dealt with the traditional C-V measurement procedure in more detail, and I described the method, what I used to evaluate my measurement results. I summarized the most improtant properties of vanadium dioxide, then I presented the preparation process of the samples used in my measurements. After that, I reported my measurement results, then I evaluated and compared them. I found that the increase of the temperature caused the C-V curves shift to the negative direction on the voltage axis, and the flat-band voltage decreases. I demonstrated that the vanadium dioxide was responsible for these effects. I determined that the work function of the vanadium dioxide increases by warming, but the phase transition can't be detected this way; the results are consistent with data from the vibrating electrode surface potential measurements.