Development of verification environment for testing general packet processing logic

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Dr. Tevesz Gábor
Department of Automation and Applied Informatics

Nowadays FPGAs are emerging in many areas that need high performance computing or fast parallel execution. In telecommunication these devices are often used for performing packet processing operations due to their reconfigurability, flexibility and their parallel nature. For FPGA development different HDL programming languages are used. The verification has improved a lot in recent decades. Verification and simulation is often necessary during the design of a complex logics in the data path. Currently UVM is one of the most used methodology for verification of HDL modules.

In my BSc. thesis I’ve constructed a general class hierarchy, which speeds up the verification process. This provides a generic framework that is easy-to-use, and gives head-start on creating testbenches even for those not familiar with UVM. In this thesis, this general class hierarchy was improved upon more complex demands. By using interface classes, I have reduced the amount of type parameters in classes that are necessary for testbench construction. I have created generic monitor and driver classes. I have made it possible to read parameters and sequences from XML files. I provided an option for easier use of UVM register model. The general framework was extended to help testing of packet processing modules: I developed classes that support generation and checking of packets, with the option of fault-injection. Capabilities of the system are presented through the verification of a VLAN to MPLS converter module.


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