The main reasons of the project are to facilitate the learning of the Verilog hardware description language for students and to make an alternative for change the currently used development environment.
By some of the subjects educated by the Department of Measurement and Information Systems the students shall make themselves familiar with the Verilog language. The teaching aid in this case is the ISE WebPACK Design Software developed by Xilinx. The size of the software is big, and it is complicated to use as for students as for teachers. These facts give cause for change the Xilinx program and find another which is created on the basis of requirements by students and teachers.
The development environment reviewed in my thesis consists of three components. The first one is an editing component, created especially for source code so it contains all the useful features for developers. The second one is a Verilog simulator. This component can create text and .vcd (Value Change Dump) file output as well, it depends on the developer. In the latter case the information in that file is useable for waveform generation. For this reason the third component of the IDE is a waveform viewer. By this component after opening the file the user will be able to do signal analysis.
Afterall the development environment can be a suitable alternative for changing the currently used program because it contains most of the functions that the students and teachers require.