Hardware acceleration of a video encoding algorithm on Zynq SOC

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Supervisor:
Raikovich Tamás
Department of Measurement and Information Systems

The purpose of the thesis was to investigate the possibility of accelerating an H.264 encoding algorithm using FPGA resources. I studies the basic video coding concepts, tools and algorithms. I reviewed the x264 software, which is the most commonly used H.264 encoder today. I conducted experiments with the x264 encoder with different samples and various settings. With the review of the x264 code and the use of dynamic program analysis tools I determined the throughput bottleneck of the software, and identified the most computationally demanding parts of the algorithm.

The other goal of this thesis was to design and implement a hardware accelerated encoder using a Xilinx Zynq System-on-Chip (SoC). With the Zynq SoC I designed and implemented a system capable of encoding videos using the Processing System and Programmable Logic of the device. While developing the whole system I encountered various abstraction level design methods from low level FPGA design, through system level software design, embedded software design to high level graphical user application development. With the integration of various custom, and pre-built system components, eventually I was able to realize a hardware accelerated H.264 video encoder. Finally I measured the speed of the video encoding algorithm with and without hardware acceleration.

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