Application of Vivado HLS synthesis

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Dr. Fehér Béla
Department of Measurement and Information Systems

In the electronics, everything is going to more complex and sophisticated: the minimum linewidth decreases, the clock speeds are accelerated, the number of embedded cores increases. Everything has changed except one thing, the RTL creating process. We would like to design our modern systems with tools and methods that are derived from the middle 1990s.

The High-Level Synthesis, which is a new design method in the engineers’ toolbar, may soon appear. This tool has previous versions from the 80’s, but so far the engineers have not been able to achieve acceptable results with them. The new design method could facilitate the engineers life and the Vivado HLS from the Xilinx sounds rather promising.

In the thesis, I examine the properties of the latest generation Xilinx’s System on Chip, namely the ZYNQ Z-7020. My research studies the Vivado HLS synthesizer operation and the application possibilities. Moreover, three image processing algorithms are mapped to the mentioned device. Furthermore, I would like to examine, through these model systems, how effectively the Vivado HLS can synthetize a specified module from a C language description to a hardware language description. Finally, I compare the completed modules’ speed with the systems that only contain a processor.


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