Implementing a Z-buffer unit in FPGA

OData support
Supervisor:
Szántó Péter
Department of Measurement and Information Systems

My task was to solve the visibility problem which is part of the three dimensional rendering. In my work I provide a survey of the used geometrical transformations during image synthesis, the math of the different steps and the different solutions to the visibility problem.

I discuss the various technologies used by different companies on the market, the developments during time and accommodation to the ever changing needs.

Thereafter I present the z-buffer module designed by me. During development I used the Xilinx ISE environment, unitized the built-in simulation to verify the functionality of my system. In my thesis I describe the different sub modules in detail, the function and the relation to each other.

My module implements segmented image rendering, the used memory is on-chip. I provide ways to read the finished segment while the module works on the next one. The maximum working frequency is 190 MHz, measured by the development environment.

In the end I mention the additional plans and solvable problems.

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