"eSchem" - Schematic visualisation tool and graphics editor application developoment in Java

OData support
Supervisor:
Dr. Pohl László
Department of Electron Devices

The complexity of modern digital integrated circuits require a thorough verification process to make sure that their desing is error-free before moving to production.

Functional verification of a hardware means checking its operation according to the hardware’s specification through an exhaustive series of tests, in an ideal case by examining all possible states. Metric verification using languages created for this purpose replaced hardware description language driven verification used beforehand.

The Cadence Incisive Enterprise Specman® Elite Testbench is a verificaiton software that automates certain steps in the semiconductor verification process and ensures the functional coverage of the hardware design on an architectural/specification level. It supports the "e" programming language, which was designed specifically with verification in mind, and UVM (Universal Verification Methodology).

Cadence stated that there are no plans to add a graphical editor tool to the software. Currently the user can browse the UVM verification environment objects and their associated information in a text based tree view (called "Data Browser").

From a productivity perspective, an interactive and easy to use graphical editor tool would be essential, which displays the object hierarchy generated by "e"-code. At present, for lack of a better alternative, hand-drawn diagrams are used, which are not only prone to error but also time consuming.

The goal was to create a Java application, which can graphically display existing verification environments, while also providing additional non-visualisable information (i.e. properties of UMV objects). I implemented the graphical user interface of the application in two versions, one using the JavaFX platform, and the other the Eclipse Rich Client Platform/Graphical Editing Framework.

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